CMSIS-Core (Cortex-A): ARMCA9.h File Reference

| CMSIS-Core (Cortex-A) Version 1.1.4 CMSIS-Core support for Cortex-A processor-based devices

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ARMCA9.h File Reference

## Macros
#define | VE_A9_MP_FLASH_BASE0 (0x00000000UL)
#define | VE_A9_MP_FLASH_BASE1 (0x0C000000UL)
#define | VE_A9_MP_SRAM_BASE (0x14000000UL)
#define | VE_A9_MP_PERIPH_BASE_CS2 (0x18000000UL)
#define | VE_A9_MP_VRAM_BASE (0x00000000UL + VE_A9_MP_PERIPH_BASE_CS2)
#define | VE_A9_MP_ETHERNET_BASE (0x02000000UL + VE_A9_MP_PERIPH_BASE_CS2)
#define | VE_A9_MP_USB_BASE (0x03000000UL + VE_A9_MP_PERIPH_BASE_CS2)
#define | VE_A9_MP_PERIPH_BASE_CS3 (0x1C000000UL)
#define | VE_A9_MP_DAP_BASE (0x00000000UL + VE_A9_MP_PERIPH_BASE_CS3)
#define | VE_A9_MP_SYSTEM_REG_BASE (0x00010000UL + VE_A9_MP_PERIPH_BASE_CS3)
#define | VE_A9_MP_SERIAL_BASE (0x00030000UL + VE_A9_MP_PERIPH_BASE_CS3)
#define | VE_A9_MP_AACI_BASE (0x00040000UL + VE_A9_MP_PERIPH_BASE_CS3)
#define | VE_A9_MP_MMCI_BASE (0x00050000UL + VE_A9_MP_PERIPH_BASE_CS3)
#define | VE_A9_MP_KMI0_BASE (0x00060000UL + VE_A9_MP_PERIPH_BASE_CS3)
#define | VE_A9_MP_UART_BASE (0x00090000UL + VE_A9_MP_PERIPH_BASE_CS3)
#define | VE_A9_MP_WDT_BASE (0x000F0000UL + VE_A9_MP_PERIPH_BASE_CS3)
#define | VE_A9_MP_TIMER_BASE (0x00110000UL + VE_A9_MP_PERIPH_BASE_CS3)
#define | VE_A9_MP_DVI_BASE (0x00160000UL + VE_A9_MP_PERIPH_BASE_CS3)
#define | VE_A9_MP_RTC_BASE (0x00170000UL + VE_A9_MP_PERIPH_BASE_CS3)
#define | VE_A9_MP_UART4_BASE (0x001B0000UL + VE_A9_MP_PERIPH_BASE_CS3)
#define | VE_A9_MP_CLCD_BASE (0x001F0000UL + VE_A9_MP_PERIPH_BASE_CS3)
#define | VE_A9_MP_PL310_BASE (0x1E00A000UL)
#define | VE_A9_MP_PRIVATE_PERIPH_BASE (0x2C000000UL)
#define | VE_A9_MP_GIC_DISTRIBUTOR_BASE (0x00001000UL + VE_A9_MP_PRIVATE_PERIPH_BASE)
#define | VE_A9_MP_GIC_INTERFACE_BASE (0x00000100UL + VE_A9_MP_PRIVATE_PERIPH_BASE)
#define | VE_A9_MP_PRIVATE_TIMER (0x00000600UL + VE_A9_MP_PRIVATE_PERIPH_BASE)
#define | VE_A9_MP_SSRAM_BASE (0x2E000000UL)
#define | VE_A9_MP_DRAM_BASE (0x80000000UL)
#define | GIC_DISTRIBUTOR_BASE VE_A9_MP_GIC_DISTRIBUTOR_BASE
#define | GIC_INTERFACE_BASE VE_A9_MP_GIC_INTERFACE_BASE
#define | TIMER_BASE VE_A9_MP_PRIVATE_TIMER
#define | L2C_310_BASE VE_A9_MP_PL310_BASE
#define | __CA_REV 0x0000U
| Contains the core revision for a Cortex-A class device. More...
#define | __CORTEX_A 9U
| Contains the core family for a Cortex-A class device. More...
#define | __FPU_PRESENT 1U /* FPU present */
#define | __GIC_PRESENT 1U /* GIC present */
#define | __TIM_PRESENT 1U /* TIM present */
#define | __L2C_PRESENT 0U /* L2C present */

## Enumerations
enum | IRQn_Type { SGI0_IRQn = 0, SGI1_IRQn = 1, SGI2_IRQn = 2, SGI3_IRQn = 3, SGI4_IRQn = 4, SGI5_IRQn = 5, SGI6_IRQn = 6, SGI7_IRQn = 7, SGI8_IRQn = 8, SGI9_IRQn = 9, SGI10_IRQn = 10, SGI11_IRQn = 11, SGI12_IRQn = 12, SGI13_IRQn = 13, SGI14_IRQn = 14, SGI15_IRQn = 15, GlobalTimer_IRQn = 27, PrivTimer_IRQn = 29, PrivWatchdog_IRQn = 30, Watchdog_IRQn = 32, Timer0_IRQn = 34, Timer1_IRQn = 35, RTClock_IRQn = 36, UART0_IRQn = 37, UART1_IRQn = 38, UART2_IRQn = 39, UART3_IRQn = 40, MCI0_IRQn = 41, MCI1_IRQn = 42, AACI_IRQn = 43, Keyboard_IRQn = 44, Mouse_IRQn = 45, CLCD_IRQn = 46, Ethernet_IRQn = 47, VFS2_IRQn = 73 }

## Macro Definition Documentation

#define __FPU_PRESENT 1U /* FPU present */

#define __GIC_PRESENT 1U /* GIC present */

#define __L2C_PRESENT 0U /* L2C present */

#define __TIM_PRESENT 1U /* TIM present */

#define GIC_DISTRIBUTOR_BASE VE_A9_MP_GIC_DISTRIBUTOR_BASE

#define GIC_INTERFACE_BASE VE_A9_MP_GIC_INTERFACE_BASE

#define L2C_310_BASE VE_A9_MP_PL310_BASE

#define TIMER_BASE VE_A9_MP_PRIVATE_TIMER

#define VE_A9_MP_AACI_BASE (0x00040000UL + VE_A9_MP_PERIPH_BASE_CS3)

(AACI ) Base Address

#define VE_A9_MP_CLCD_BASE (0x001F0000UL + VE_A9_MP_PERIPH_BASE_CS3)

(CLCD ) Base Address

#define VE_A9_MP_DAP_BASE (0x00000000UL + VE_A9_MP_PERIPH_BASE_CS3)

(LOCAL DAP ) Base Address

#define VE_A9_MP_DRAM_BASE (0x80000000UL)

(DRAM ) Base Address

#define VE_A9_MP_DVI_BASE (0x00160000UL + VE_A9_MP_PERIPH_BASE_CS3)

(DVI ) Base Address

#define VE_A9_MP_ETHERNET_BASE (0x02000000UL + VE_A9_MP_PERIPH_BASE_CS2)

(ETHERNET ) Base Address

#define VE_A9_MP_FLASH_BASE0 (0x00000000UL)

(FLASH0 ) Base Address

#define VE_A9_MP_FLASH_BASE1 (0x0C000000UL)

(FLASH1 ) Base Address

#define VE_A9_MP_GIC_DISTRIBUTOR_BASE (0x00001000UL + VE_A9_MP_PRIVATE_PERIPH_BASE)

(GIC DIST ) Base Address

#define VE_A9_MP_GIC_INTERFACE_BASE (0x00000100UL + VE_A9_MP_PRIVATE_PERIPH_BASE)

(GIC CPU IF ) Base Address

#define VE_A9_MP_KMI0_BASE (0x00060000UL + VE_A9_MP_PERIPH_BASE_CS3)

(KMI0 ) Base Address

#define VE_A9_MP_MMCI_BASE (0x00050000UL + VE_A9_MP_PERIPH_BASE_CS3)

(MMCI ) Base Address

#define VE_A9_MP_PERIPH_BASE_CS2 (0x18000000UL)

(Peripheral ) Base Address

#define VE_A9_MP_PERIPH_BASE_CS3 (0x1C000000UL)

(Peripheral ) Base Address

#define VE_A9_MP_PL310_BASE (0x1E00A000UL)

(L2C-310 ) Base Address

#define VE_A9_MP_PRIVATE_PERIPH_BASE (0x2C000000UL)

(Peripheral ) Base Address

#define VE_A9_MP_PRIVATE_TIMER (0x00000600UL + VE_A9_MP_PRIVATE_PERIPH_BASE)

(PTIM ) Base Address

#define VE_A9_MP_RTC_BASE (0x00170000UL + VE_A9_MP_PERIPH_BASE_CS3)

(RTC ) Base Address

#define VE_A9_MP_SERIAL_BASE (0x00030000UL + VE_A9_MP_PERIPH_BASE_CS3)

(SERIAL ) Base Address

#define VE_A9_MP_SRAM_BASE (0x14000000UL)

(SRAM ) Base Address

#define VE_A9_MP_SSRAM_BASE (0x2E000000UL)

(System SRAM) Base Address

#define VE_A9_MP_SYSTEM_REG_BASE (0x00010000UL + VE_A9_MP_PERIPH_BASE_CS3)

(SYSTEM REG ) Base Address

#define VE_A9_MP_TIMER_BASE (0x00110000UL + VE_A9_MP_PERIPH_BASE_CS3)

(TIMER ) Base Address

#define VE_A9_MP_UART4_BASE (0x001B0000UL + VE_A9_MP_PERIPH_BASE_CS3)

(UART4 ) Base Address

#define VE_A9_MP_UART_BASE (0x00090000UL + VE_A9_MP_PERIPH_BASE_CS3)

(UART ) Base Address

#define VE_A9_MP_USB_BASE (0x03000000UL + VE_A9_MP_PERIPH_BASE_CS2)

(USB ) Base Address

#define VE_A9_MP_VRAM_BASE (0x00000000UL + VE_A9_MP_PERIPH_BASE_CS2)

(VRAM ) Base Address

#define VE_A9_MP_WDT_BASE (0x000F0000UL + VE_A9_MP_PERIPH_BASE_CS3)

(WDT ) Base Address

## Enumeration Type Documentation

enum IRQn_Type

Device specific Interrupt IDs

Enumerator
SGI0_IRQn | Software Generated Interrupt 0
SGI1_IRQn | Software Generated Interrupt 1
SGI2_IRQn | Software Generated Interrupt 2
SGI3_IRQn | Software Generated Interrupt 3
SGI4_IRQn | Software Generated Interrupt 4
SGI5_IRQn | Software Generated Interrupt 5
SGI6_IRQn | Software Generated Interrupt 6
SGI7_IRQn | Software Generated Interrupt 7
SGI8_IRQn | Software Generated Interrupt 8
SGI9_IRQn | Software Generated Interrupt 9
SGI10_IRQn | Software Generated Interrupt 10
SGI11_IRQn | Software Generated Interrupt 11
SGI12_IRQn | Software Generated Interrupt 12
SGI13_IRQn | Software Generated Interrupt 13
SGI14_IRQn | Software Generated Interrupt 14
SGI15_IRQn | Software Generated Interrupt 15
GlobalTimer_IRQn | Global Timer Interrupt
PrivTimer_IRQn | Private Timer Interrupt
PrivWatchdog_IRQn | Private Watchdog Interrupt
Watchdog_IRQn | SP805 Interrupt
Timer0_IRQn | SP804 Interrupt
Timer1_IRQn | SP804 Interrupt
RTClock_IRQn | PL031 Interrupt
UART0_IRQn | PL011 Interrupt
UART1_IRQn | PL011 Interrupt
UART2_IRQn | PL011 Interrupt
UART3_IRQn | PL011 Interrupt
MCI0_IRQn | PL180 Interrupt (1st)
MCI1_IRQn | PL180 Interrupt (2nd)
AACI_IRQn | PL041 Interrupt
Keyboard_IRQn | PL050 Interrupt
Mouse_IRQn | PL050 Interrupt
CLCD_IRQn | PL111 Interrupt
Ethernet_IRQn | SMSC_91C111 Interrupt
VFS2_IRQn | VFS2 Interrupt