CMSIS-Core (Cortex-A): Interrupts and Exceptions

| CMSIS-Core (Cortex-A) Version 1.1.4 CMSIS-Core support for Cortex-A processor-based devices

- Main Page
- Usage and Description
- Reference

All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
Content | Functions
Interrupts and Exceptions

Generic functions to access the Interrupt Controller. More...

## Content
| IRQ Mode Bit-Masks
| Configure interrupt line mode.
| IRQ Priority Bit-Masks
| Definitions used by interrupt priority functions.

## Functions
int32_t | IRQ_Initialize (void)
| Initialize interrupt controller. More...
int32_t | IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler)
| Register interrupt handler. More...
IRQHandler_t | IRQ_GetHandler (IRQn_ID_t irqn)
| Get the registered interrupt handler. More...
int32_t | IRQ_Enable (IRQn_ID_t irqn)
| Enable interrupt. More...
int32_t | IRQ_Disable (IRQn_ID_t irqn)
| Disable interrupt. More...
uint32_t | IRQ_GetEnableState (IRQn_ID_t irqn)
| Get interrupt enable state. More...
int32_t | IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode)
| Configure interrupt request mode. More...
uint32_t | IRQ_GetMode (IRQn_ID_t irqn)
| Get interrupt mode configuration. More...
IRQn_ID_t | IRQ_GetActiveIRQ (void)
| Get ID number of current interrupt request (IRQ). More...
IRQn_ID_t | IRQ_GetActiveFIQ (void)
| Get ID number of current fast interrupt request (FIQ). More...
int32_t | IRQ_EndOfInterrupt (IRQn_ID_t irqn)
| Signal end of interrupt processing. More...
int32_t | IRQ_SetPending (IRQn_ID_t irqn)
| Set interrupt pending flag. More...
uint32_t | IRQ_GetPending (IRQn_ID_t irqn)
| Get interrupt pending flag. More...
int32_t | IRQ_ClearPending (IRQn_ID_t irqn)
| Clear interrupt pending flag. More...
int32_t | IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority)
| Set interrupt priority value. More...
uint32_t | IRQ_GetPriority (IRQn_ID_t irqn)
| Get interrupt priority. More...
int32_t | IRQ_SetPriorityMask (uint32_t priority)
| Set priority masking threshold. More...
uint32_t | IRQ_GetPriorityMask (void)
| Get priority masking threshold. More...
int32_t | IRQ_SetPriorityGroupBits (uint32_t bits)
| Set priority grouping field split point. More...
uint32_t | IRQ_GetPriorityGroupBits (void)
| Get priority grouping field split point. More...

## Description

This section describes the device agnostic interrupt API viable for a wide range of specific interrupt controllers. The IRQ Controller API allows interrupt dependend applications to be easily portable across a wide range of controllers.

Note
  The default implementation for Arm GIC (Generic Interrupt Controller) can be found in irq_ctrl_gic.c. It uses `weak` functions thus it can easily be overwritten by an alternative user implementation if needed.

The Armv7-A architecture defines a common set of first level exceptions, see table below.

Exception | CMSIS Handler | Offset | Description
--- | --- | --- | ---
Reset | Reset_Handler | 0x0000 | First instruction executed after reset.
Undefined Instruction (Undef) | Undef_Handler | 0x0004 | Signals usage of an illegal instructions.
Supervisor Call (SVC) | SVC_Handler | 0x0008 | Issued by software using SVC instruction.
Prefetch Abort (PAbt) | PAbt_Handler | 0x000C | Signals a memory abort on istruction fetch.
Data Abort (DAbt) | DAbt_Handler | 0x0010 | Signals a memory abort on data read or write.
Hyp Trap | (NOP) | 0x0014 | Hypervisor instruction trap, only available with Virtualization Extensions.
IRQ interrupt | IRQ_Handler | 0x0018 | Interrupt Request (typically from Interrupt Controller)
FIQ interrupt | FIQ_Handler | 0x001C | Fast Interrupt Request (typically from Interrupt Controller)

By default those handlers are defined as weak empty functions by the device specific startup code. Software and peripheral interrupts are all handled by one of the both central interrupt handlers (IRQ and FIQ). These needs to be implemented application specific. If an RTOS is used the interrupt handlers are typically provided by the RTOS, e.g. when using RTX5.

The interrupts available depends on the actual device in use. According to CMSIS specification the interrupts are defined as IRQn_Type in Device Header File <device.h>. Using the generic IRQ API one can easily enable and disable interrupts, set up priorities, modes and preemption rules, and register interrupt callbacks.

Example:

void SGI0_Handler() {
/*
* Handle Interrupt
*/
IRQ_ClearPending((IRQn_ID_t)SGI0_IRQn);
}
void main() {
/* Initialize the Interrupt Controller */
IRQ_Initialize();
/* Register the user defined handler function */
IRQ_SetHandler((IRQn_ID_t)SGI0_IRQn, SGI0_Handler);
/* Set the priority considering the priority grouping */
const uint32_t subprio = IRQ_GetPriorityGroupBits();
IRQ_SetPriority((IRQn_ID_t)SGI0_IRQn, 1u << subprio);
/* Set interrupt mode to falling edge */
IRQ_SetMode((IRQn_ID_t)SGI0_IRQn, IRQ_MODE_TYPE_IRQ | IRQ_MODE_CPU_0 | IRQ_MODE_TRIG_EDGE | IRQ_MODE_TRIG_EDGE_FALLING);
IRQ_Enable((IRQn_ID_t)SGI0_IRQn);
/* Trigger interrupt */
IRQ_SetPending((IRQn_ID_t)SGI0_IRQn);
IRQ_Disable((IRQn_ID_t)SGI0_IRQn);
}

## Function Documentation

int32_t IRQ_ClearPending | ( | IRQn_ID_t | irqn | ) |

Parameters

  [in] | irqn | interrupt ID number

Returns
  0 on success, -1 on error.

This function clears the pending status of the interrupt identified by the irqn parameter.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 16) && (irqn < IRQ_GIC_LINE_COUNT)) {
GIC_ClearPendingIRQ ((IRQn_Type)irqn);
status = 0;
} else {
status = -1;
}
return (status);
}

int32_t IRQ_Disable | ( | IRQn_ID_t | irqn | ) |

Parameters

  [in] | irqn | interrupt ID number

Returns
  0 on success, -1 on error.

This function disables forwarding of the corresponding interrupt to the CPU.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_Disable (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
GIC_DisableIRQ ((IRQn_Type)irqn);
status = 0;
} else {
status = -1;
}
return (status);
}

int32_t IRQ_Enable | ( | IRQn_ID_t | irqn | ) |

Parameters

  [in] | irqn | interrupt ID number

Returns
  0 on success, -1 on error.

This function enables forwarding of the corresponding interrupt to the CPU.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_Enable (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
GIC_EnableIRQ ((IRQn_Type)irqn);
status = 0;
} else {
status = -1;
}
return (status);
}

int32_t IRQ_EndOfInterrupt | ( | IRQn_ID_t | irqn | ) |

Parameters

  [in] | irqn | interrupt ID number

Returns
  0 on success, -1 on error.

This function informs the interrupt controller that the interrupt service routine processing of the currently active interrupt request is completed.

The parameter irqn should specify the value previously returned by the IRQ_GetActiveIRQ or IRQ_GetActiveFIQ functions.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
GIC_EndInterrupt ((IRQn_Type)irqn);
if (irqn == 0) {
IRQ_ID0 = 0U;
}
status = 0;
} else {
status = -1;
}
return (status);
}

IRQn_ID_t IRQ_GetActiveFIQ | ( | void |  | ) |

Returns
  interrupt ID number.

This function retrieves the interrupt ID number of current FIQ source and acknowledges the interrupt.

For Arm GIC the default implementation looks like the following example:

IRQn_ID_t IRQ_GetActiveFIQ (void) {
// FIQ is not supported, return invalid ID
return ((IRQn_ID_t)-1);
}

IRQn_ID_t IRQ_GetActiveIRQ | ( | void |  | ) |

Returns
  interrupt ID number.

This function retrieves the interrupt ID number of current IRQ source and acknowledges the interrupt.

For Arm GIC the default implementation looks like the following example:

IRQn_ID_t IRQ_GetActiveIRQ (void) {
IRQn_ID_t irqn;
irqn = (IRQn_ID_t)GIC_AcknowledgePending();
return (irqn);
}

uint32_t IRQ_GetEnableState | ( | IRQn_ID_t | irqn | ) |

Parameters

  [in] | irqn | interrupt ID number

Returns
  0 - interrupt is disabled, 1 - interrupt is enabled.

This function retrieves the interrupt enable status of the interrupt identified by the irqn parameter.

Interrupt enable status can be either disabled (0) or enabled (1). Disabled status is returned for interrupts which cannot be identified by irqn.

For Arm GIC the default implementation looks like the following example:

uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
uint32_t enable;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
} else {
enable = 0U;
}
return (enable);
}

IRQHandler_t IRQ_GetHandler | ( | IRQn_ID_t | irqn | ) |

Parameters

  [in] | irqn | interrupt ID number

Returns
  registered interrupt handler function address.

This function retrieves address of the interrupt handler callback function corresponding to the specified interrupt ID number.

For Arm GIC the default implementation looks like the following example:

IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
IRQHandler h;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
h = IRQTable[irqn];
} else {
h = (IRQHandler_t)0;
}
return (h);
}

uint32_t IRQ_GetMode | ( | IRQn_ID_t | irqn | ) |

Parameters

  [in] | irqn | interrupt ID number

Returns
  current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.

This function retrieves interrupt mode configuration of the interrupt identified by the irqn parameter. IRQ_MODE_ERROR is returned for interrupts which cannot be identified by irqn.

For Arm GIC the default implementation looks like the following example:

uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
uint32_t mode;
uint32_t val;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
mode = IRQ_MODE_TYPE_IRQ;
// Get trigger mode
val = GIC_GetConfiguration((IRQn_Type)irqn);
if ((val & 2U) != 0U) {
// Corresponding interrupt is edge triggered
mode |= IRQ_MODE_TRIG_EDGE;
} else {
// Corresponding interrupt is level triggered
mode |= IRQ_MODE_TRIG_LEVEL;
}
// Get interrupt CPU targets
mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
} else {
mode = IRQ_MODE_ERROR;
}
return (mode);
}

uint32_t IRQ_GetPending | ( | IRQn_ID_t | irqn | ) |

Parameters

  [in] | irqn | interrupt ID number

Returns
  0 - interrupt is not pending, 1 - interrupt is pending.

This function retrieves the pending status of the interrupt identified by the irqn parameter.

Interrupt pending status can be either not pending (0) or pending (1). Not pending status is returned for interrupts which cannot be identified by irqn.

For Arm GIC the default implementation looks like the following example:

uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
uint32_t pending;
if ((irqn >= 16) && (irqn < IRQ_GIC_LINE_COUNT)) {
pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
} else {
pending = 0U;
}
return (pending & 1U);
}

uint32_t IRQ_GetPriority | ( | IRQn_ID_t | irqn | ) |

Parameters

  [in] | irqn | interrupt ID number

Returns
  current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.

This function retrieves the priority of the interrupt identified by the irqn parameter.

The valid priority value can be from zero (0) to the value of IRQ_PRIORITY_Msk. IRQ_PRIORITY_ERROR bit is set in returned value for interrupts which cannot be identified by irqn.

For Arm GIC the default implementation looks like the following example:

uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
uint32_t priority;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
priority = GIC_GetPriority ((IRQn_Type)irqn);
} else {
priority = IRQ_PRIORITY_ERROR;
}
return (priority);
}

uint32_t IRQ_GetPriorityGroupBits | ( | void |  | ) |

Returns
  current number of MSB bits included in the group priority field comparison with optional IRQ_PRIORITY_ERROR bit set.

This function retrieves the number of MSB bits used to determine whether a pending interrupt has sufficient priority to preempt a currently active interrupt.

IRQ_PRIORITY_ERROR value is returned when priority grouping is not supported.

For Arm GIC the default implementation looks like the following example:

uint32_t IRQ_GetPriorityGroupBits (void) {
uint32_t bp;
bp = GIC_GetBinaryPoint() & 0x07U;
return (7U - bp);
}

uint32_t IRQ_GetPriorityMask | ( | void |  | ) |

Returns
  current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.

This function retrieves the priority masking threshold for the current processor.

IRQ_PRIORITY_ERROR value is returned if priority masking is not supported.

For Arm GIC the default implementation looks like the following example:

uint32_t IRQ_GetPriorityMask (void) {
return GIC_GetInterfacePriorityMask();
}

int32_t IRQ_Initialize | ( | void |  | ) |

Returns
  0 on success, -1 on error.

This function initializes interrupt controller.

It disables all interrupt sources, clears all pending interrupts, sets interrupt priorities to highest priority and configures priority mask to lowest priority. IRQ and FIQ signal lines should be enabled and all interrupt handlers should be set to NULL.

For Arm GIC the default implementation looks like the following example:

#ifndef IRQ_GIC_LINE_COUNT
#define IRQ_GIC_LINE_COUNT (1020U)
#endif
static IRQHandler IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
int32_t IRQ_Initialize (void) {
uint32_t i;
for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
IRQTable[i] = (IRQHandler)NULL;
}
GIC_Enable();
return (0);
}

int32_t IRQ_SetHandler | ( | IRQn_ID_t | irqn,
|  | IRQHandler_t | handler
| ) |  |

Parameters

  [in] | irqn | interrupt ID number
  [in] | handler | interrupt handler function address

Returns
  0 on success, -1 on error.

This function registers address of the interrupt handler callback function corresponding to the specified interrupt ID number.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
IRQTable[irqn] = handler;
status = 0;
} else {
status = -1;
}
return (status);
}

int32_t IRQ_SetMode | ( | IRQn_ID_t | irqn,
|  | uint32_t | mode
| ) |  |

Parameters

  [in] | irqn | interrupt ID number
  [in] | mode | mode configuration

Returns
  0 on success, -1 on error.

This function configures the interrupt triggering mode, type, secure access and target CPUs of the interrupt (see IRQ Mode Bit-Masks) identified by the irqn parameter.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
int32_t status;
uint32_t val;
uint8_t cfg;
uint8_t secure;
uint8_t cpu;
status = 0;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
// Check triggering mode
val = (mode & IRQ_MODE_TRIG_Msk);
if (val == IRQ_MODE_TRIG_LEVEL) {
cfg = 0x00U;
} else if (val == IRQ_MODE_TRIG_EDGE) {
cfg = 0x02U;
} else {
status = -1;
}
// Check interrupt type
val = mode & IRQ_MODE_TYPE_Msk;
if (val != IRQ_MODE_TYPE_IRQ) {
status = -1;
}
// Check interrupt domain
val = mode & IRQ_MODE_DOMAIN_Msk;
if (val == IRQ_MODE_DOMAIN_NONSECURE) {
secure = 0;
} else {
// Check security extensions support
val = GIC_DistributorInfo() & (1UL << 10U);
if (val != 0U) {
// Security extensions are supported
secure = 1;
} else {
status = -1;
}
}
// Check interrupt CPU targets
val = mode & IRQ_MODE_CPU_Msk;
if (val == IRQ_MODE_CPU_ALL) {
cpu = 0xFF;
} else {
cpu = val >> IRQ_MODE_CPU_Pos;
}
// Apply configuration if no mode error
if (status == 0) {
GIC_SetConfiguration((IRQn_Type)irqn, cfg);
GIC_SetTarget ((IRQn_Type)irqn, cpu);
if (secure != 0U) {
GIC_SetGroup ((IRQn_Type)irqn, secure);
}
}
}
return (status);
}

int32_t IRQ_SetPending | ( | IRQn_ID_t | irqn | ) |

Parameters

  [in] | irqn | interrupt ID number

Returns
  0 on success, -1 on error.

This function sets the pending status of the interrupt identified by the irqn parameter.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_SetPending (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
GIC_SetPendingIRQ ((IRQn_Type)irqn);
status = 0;
} else {
status = -1;
}
return (status);
}

int32_t IRQ_SetPriority | ( | IRQn_ID_t | irqn,
|  | uint32_t | priority
| ) |  |

Parameters

  [in] | irqn | interrupt ID number
  [in] | priority | interrupt priority value

Returns
  0 on success, -1 on error.

This function sets the priority of the interrupt identified by the irqn parameter.

Higher priority numbers have lower priority. The highest interrupt priority has priority value 0, while the lowest value depends on the number of implemented priority levels.

The number of implemented priority bits can be determined by setting value IRQ_PRIORITY_Msk to arbitrary irqn and by retrieving the actual stored value with IRQ_GetPriority function.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
int32_t status;
if ((irqn >= 0) && (irqn < IRQ_GIC_LINE_COUNT)) {
GIC_SetPriority ((IRQn_Type)irqn, priority);
status = 0;
} else {
status = -1;
}
return (status);
}

int32_t IRQ_SetPriorityGroupBits | ( | uint32_t | bits | ) |

Parameters

  [in] | bits | number of MSB bits included in the group priority field comparison

Returns
  0 on success, -1 on error.

This function sets the number of MSB priority bits used to determine whether a pending interrupt has sufficient priority to preempt a currently active interrupt.

The number of implemented group priority bits can be determined by setting value IRQ_PRIORITY_Msk and by retrieving the actual stored value with IRQ_GetPriorityGroupBits function. Function returns error status -1 if priority grouping is not supported.

For Arm GIC the default implementation looks like the following example:

int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
int32_t status;
if (bits == IRQ_PRIORITY_Msk) {
bits = 7U;
}
if (bits < 8U) {
GIC_SetBinaryPoint (7U - bits);
status = 0;
} else {
status = -1;
}
return (status);
}

int32_t IRQ_SetPriorityMask | ( | uint32_t | priority | ) |

Parameters

  [in] | priority | priority masking threshold value

Returns
  0 on success, -1 on error.

This function sets the priority masking threshold for the current processor.

It ensures that only interrupts with a higher priority than priority threshold value are signaled to the target processor. Function returns error status -1 if priority masking is not supported.

For Arm GIC the default implementation looks like the following example:

IRQ_SetPriorityMask (uint32_t priority) {
GIC_SetInterfacePriorityMask (priority);
return (0);
}